The exposure tool is a critical enabler to continue improving the packing density and transistor speed in the semiconductor industry. In addition to increasing resolution, which improves packing density and transistor speed, a scanner is also expected to provide tight line width control across the chip (ACLV). ACLV has a significant influence on circuit speed. Contribution of the lithographic sources of error to the final CD variation across chip and wafer will be discussed in this paper. CD control afforded by the future optical lithography tools is estimated using Monte Carlo aerial image simulations by making reasonable assumptions about the performance of the future tools. The main sources of CD error can be identified. This approach will help identify the path to improving CD control. The technique described was tested using data from a present technology generation and reasonable agreement between predicted and observed CD variation was achieved.