We have developed hardware architecture for implementation of multiuser detector considering different types of multiply/accumulate units realized on RSFQ logic/memory family. Asynchronous operation naturally supports shifting over zero technique that increases the speed of the serial multiplier on 30% and at the same time decreases Josephson junction count. It also essential for construction spreading code generator to minimize the time required for initialization. Both devices were designed to operate at targeting clock speed 54 GHz for an 1.5 um TRW' fabrication process .