In few years CMOS devices will be operated by gates in the sub 30 nm dimension regime. The gate patterning step will be one of the key issue of the device fabrication process since the variation in gate dimension must not exceed the nominal critical dimension (CD) targeted by few nm. Advanced patterning studies are currently conducted in research groups to define the best strategy for manufacturing.

In a standard approach with silicon on a thin gate oxide, the gate stack patterning process has to address severe requirements:

1. define a gate where the final dimension is smaller than the resolution printed in the resist after lithography. Several strategies are investigated such as generating a "notched gate" by lateral erosion of silicon or resist trimming in oxygen-based plasmas followed by anisotropic etching in silicon . We will pont out the limitations of these two strategies.
2. control the CD of the gate by few nm only when entering in the sub 30 nm regime. We will demonstrate that the CD control is impacted by each single step of the gate stack patterning process. We will bring evidence that the final CD deviation of the gate depends on
   • the hard mask opening
   • the sidewall passivation layer thickness impacted by the plasma chemistry and aspect ratio of the silicon gates
   • the "notch" capability of the landing step to eliminate the silicon foot formed at the edge of the gate during the main etch step of the process

The gate patterning results are obtained in a state of the art ICP industrial etch chamber. The mechanisms involved in the gate patterning processes presented will be discussed and illustrated by surface analyses studies using XPS, mass spectrometry data, optical emission studies, high resolution SEM and real time ellipsometry.