MOSFET devices have been aggressively scaled to improve performance, but the continuing push to decrease device feature size is limited by some of the physical properties of the current materials. Current technology forecasts show that deep sub-micron device scaling will soon require SiO2 gate dielectrics to be scaled to much less than 2 nm. It is generally accepted that such scaling will lead to increased tunneling currents from these very thin SiO2 gate dielectrics resulting in an unacceptable power consumption and decreased reliability. One alternative is to replace SiO2 with a material having a higher dielectric constant that will allow the use of a thicker, and therefore less leaky, gate dielectric. Towards this end, high dielectric constant metal-oxide materials calculated to be thermodynamically stable against silicon, have been evaluated to replace SiO2 as a gate dielectric with the desire to preserve a conventional device fabrication process. However, even though thermodynamic calculations using bulk material data do not predict a reaction for the evaluated metal-oxides with silicon or SiH4, at process temperatures used, incompatibilities or adverse reactions are often observed. Results of investigations to circumvent the observed adverse reaction with the conventional poly-Si process using a metal oxide gate dielectric, as well as alternate schemes for silicon gate processing and gate materials will be reported.