Traditional scaling of CMOS (complimentary metal-oxide-semiconductor), over the past 25 years or so, has allowed the semiconductor industry grow at a more or less constant rate (Moore's curve). Unfortunately, within the last few years, this scaling has been found to be increasingly difficult. With the shrinking device dimension, so- called 2 dimensional short-channel effects can limit the reduction of the gate length. As device dimensions are reduced, the thickness of the gate dielectric must also be reduced to maintain or increase the capacitance C= e_o x e_oxide / t_oxide, where t_oxide and e_oxide are the oxide thickness and permittivity and e_o is the dielectric permittivity of free space. To first order, the drive current of an MOSFET (metal-oxide-semiconductor field-effect transistor), and therefore the device speed, is proportional to the gate capacitance. Higher capacitance, given by thinner dielectric films, leads to higher drive currents and faster devices. However, as the thickness of the gate dielectric is reduced, the leakage current starts to impact the device operation and reliability. For SiO₂ the leakage current starts to have an extremely large effect once the thickness < ~20 Å. For most of the technologies that are in development, the gate dielectric thickness is well below 20 Å.

The capacitance of the FET is the total gate capacitance, which contains not only the gate dielectric or oxide capacitance, but also any other stray capacitance(s) which may be due to the poly-crystalline silicon gate (poly-Si), the substrate, spacers, sidewalls, etc. which are highly dependent upon device design and processing. With the decreasing dielectric thickness and a relatively constant gate bias, silicon surface potential (field) increases. The poly-Si, which was previously acting as a metal, now behaves more like a semiconductor. As the surface potential increases, the high surface field begins to deplete the poly-Si of carriers, and producing a depletion capacitance. This effect is known as poly depletion and it is this effect that is partially responsible for lower than expected drive current and device speed. One method of removing poly deletion effect is to replace the poly-Si with a metal.

The implementation of metals, into a CMOS process, however, is anything but a straightforward process. Firstly, one would need two metals, not one, to replace the p+ and n+ dopants used for making complementary devices. One such metal, to replace the n+ gate should have a work function of the order of the electron affinity of silicon, i.e. near the conduction band edge. The other metal (for the pFET) would need a work function towards the silicon valence band edge. Device design would dictate exactly what work function would be required.

With the choice of the metals not only need the work function be taken into account, but also the integration of these metals into a CMOS process, and all it entails, quickly becomes one of, if not the, dominant issue.

In the current literature, many metals, metallic alloys and metal nitrides that have been proposed as candidate gate material. In this work I will discuss some of the issues regarding the choice of metallic gate material with respect its work function, its effect on device properties and the difficulties one must overcome to produce higher performance FETs.